Memory device

ABSTRACT

A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending, commonlyassigned U.S. patent applications: “DEAPROM HAVING AMORPHOUS SILICONCARBIDE GATE INSULATOR,” Ser. No. 08/902,843, “DEAPROM AND TRANSISTORWITH GALLIUM NITRIDE OR GALLIUM ALUMINUM NITRIDE GATE,” Ser. No.08/902,098, “CARBURIZED SILICON GATE INSULATORS FOR INTEGRATEDCIRCUITS,” Ser. No. 08/903,453, “SILICON CARBIDE GATE TRANSISTOR ANDFABRICATION PROCESS,” Ser. No. 08/903,486, “TRANSISTOR WITH VARIABLEELECTRON AFFINITY GATE AND METHODS OF FABRICATION AND USE,” Ser. No.08/903,452, and “TRANSISTOR WITH SILICON OXYCARBIDE GATE AND METHODS OFFABRICATION AND USE,” Ser. No. 08/902,132 each of which is filed on evendate herewith, and each of which disclosure is herein incorporated byreference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuittechnology, including dynamic random access memories (DRAMs) andelectrically erasable and programmable read only memories (EEPROMS), andparticularly to a floating gate transistor memory that is dynamicallyelectrically alterable and programmable, and methods of fabrication anduse.

BACKGROUND OF THE INVENTION

Dynamic random access memories (DRAMs) are data storage devices thatstore data as charge on a storage capacitor. A DRAM typically includesan array of memory cells. Each memory cell includes a storage capacitorand an access transistor for transferring charge to and from the storagecapacitor. Each memory cell is addressed by a word line and accessed bya bit line. The word line controls the access transistor such that theaccess transistor controllably couples and decouples the storagecapacitor to and from the bit line for writing and reading data to andfrom the memory cell.

The storage capacitor must have a capacitance that is large enough toretain a charge sufficient to withstand the effects of parasiticcapacitances, noise due to circuit operation, and access transistorreverse-bias junction leakage currents between periodic data refreshes.Such effects can result in erroneous data. Obtaining a large capacitancetypically requires a storage capacitor having a large area. However, amajor goal in DRAM design is to minimize the area of a DRAM memory cellto allow cells to be more densely packed on an integrated circuit die sothat more data can be stored on smaller integrated circuits.

In achieving the goal of increasing DRAM array capacity by increasingcell density, the sufficient capacitance levels of the DRAM storagecapacitors must be maintained. A “stacked storage cell” design canincrease the cell density to some degree. In this technique, two or morecapacitor conductive plate layers, such as polycrystalline silicon(polysilicon or poly), are deposited over a memory cell accesstransistor on a semiconductor wafer. A high dielectric constant materialis sandwiched between these capacitor plate layers. Such a capacitorstructure is known as a stacked capacitor cell (STC) because the storagecapacitor plates are stacked on top of the access transistor. However,formation of stacked capacitors typically requires complicated processsteps. Stacked capacitors also typically increase topographical featuresof the integrated circuit die, making subsequent lithography andprocessing, such as for interconnection formation, more difficult.Alternatively, storage capacitors can be formed in deep trenches in thesemiconductor substrate, but such trench storage capacitors also requireadditional process complexity. There is a need in the art to furtherincrease memory storage density without adding process complexity oradditional topography.

Electrically erasable and programmable read only memories (EEPROMs)provide nonvolatile data storage. EEPROM memory cells typically usefield-effect transistors (FETs) having an electrically isolated(floating) gate that affects conduction between source and drain regionsof the FET. A gate dielectric is interposed between the floating gateand an underlying channel region between source and drain regions. Acontrol gate is provided adjacent to the floating gate, separatedtherefrom by an intergate dielectric.

In such memory cells, data is represented by charge stored on thepolysilicon floating gates, such as by hot electron injection orFowler-Nordheim tunneling during a write operation. Fowler-Nordheimtunneling is typically used to remove charge from the polysiliconfloating gate during an erase operation. However, the relatively largeelectron affinity of the polysilicon floating gate presents a relativelylarge tunneling barrier energy at its interface with the underlying gatedielectric. The large tunneling barrier energy provides longer dataretention times than realistically needed. For example, a data chargeretention time at 85° C. is estimated to be in millions of years forsome floating gate memory devices. The large tunneling barrier energyalso increases the voltages and time needed to store and remove chargeto and from the polysilicon floating gate. “Flash” EEPROMs, which havean architecture that allows the simultaneous erasure of many floatinggate transistor memory cells, require even longer erasure times toaccomplish this simultaneous erasure. The large erasure voltages neededcan result in hole injection into the gate dielectric. This can causeerratic overerasure, damage to the gate dielectric, and introduction oftrapping states in the gate dielectric. The high electric fields thatresult from the large erasure voltages can also result in reliabilityproblems, leading to device failure. There is a need in the art toobtain floating gate transistors that allow the use of lower programmingand erasure voltages and shorter programming and erasure times.

REFERENCES

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SUMMARY OF THE INVENTION

The present invention includes a memory cell that allows the use oflower programming and erasure voltages and shorter programming anderasure times by providing a storage electrode for storing charge andproviding an adjacent insulator having a barrier energy with the storageelectrode of less than approximately 3.3 eV. According to one aspect ofthe invention, the barrier energy can be established at a predeterminedvalue by selecting various materials for the storage electrode and theinsulator, such as to obtain a desired data charge retention time, anerase time, or an erase voltage. In one embodiment, the insulator has alarger electron affinity than silicon dioxide. In another embodiment,the storage electrode has a smaller electron affinity thanpolycrystalline silicon.

In one embodiment, the memory cell includes a floating gate transistor,having a barrier energy between the floating gate and an insulator ofless than approximately 3.3 eV, such as obtained by selecting thematerials of the floating gate and the insulator. According to anotheraspect of the present invention, the transistor is adapted for dynamicrefreshing of charge stored on the floating gate. A refresh circuitallows dynamic refreshing of charge stored on the floating gate. Thebarrier energy can be lowered to a desired value by selecting theappropriate material composition of the floating gate. As a result,lower programming and erasure voltages and shorter programming anderasure times are obtained.

Another aspect of the present invention provides a method of using afloating gate transistor having a barrier energy of less thanapproximately 3.3 eV at an interface between a floating gate electrodeand an adjacent insulator. Data is stored by changing the charge of thefloating gate. Data is refreshed based on a data charge retention timeestablished by the barrier energy. Data is read by detecting aconductance between a source and a drain. The large transconductancegain of the memory cell of the present invention provides a more easilydetected signal and reduces the required data storage capacitance valueand memory cell size when compared to a conventional dynamic randomaccess memory (DRAM) cell.

The present invention also includes a method of forming a floating gatetransistor. Source and drain regions are formed. Materials are selectedfor a floating gate and a gate insulator such that a barrier energy atan interface therebetween is less than approximately 3.3 eV. A gateinsulator is formed from the gate insulator material. A floating gate isformed from the gate material, such that the floating gate is isolatedfrom conductors and semiconductors. According to one aspect of thepresent invention, the floating gate and gate insulator materials areselected based on a desired data charge retention time. If the chargestored on the floating gate is refreshed, the floating gate and gateinsulator materials can be selected to obtain a relatively short datacharge retention time, thereby obtaining the advantages of shorterwrite/programming and erase times. The shorter write/programming anderase times make operation of the present memory speed competitive witha DRAM.

The present invention also includes a memory device that is capable ofproviding short programming and erase times, low programming and erasevoltages, and lower electric fields in the memory cell for improvedreliability. The memory device includes a plurality of memory cells.Each memory cell includes a transistor. Each transistor includes asource region, a drain region, a channel region between the source anddrain regions, and a floating gate that is separated from the channelregion by an insulator. An interfacial barrier energy between thefloating gate and the insulator is less than approximately 3.3 eV. Thetransistor also includes a control gate located adjacent to the floatinggate and separated therefrom by an intergate dielectric. The memorydevice includes flash electrically erasable and programmable read onlymemory (EEPROM), dynamic random access memory (DRAM), and dynamicallyelectrically alterable and programmable read only memory (DEAPROM)embodiments.

The memory cell of the present invention, having a barrier energybetween the floating electrode and the insulator that is lower than thebarrier energy between polysilicon and SiO₂, provides largetransconductance gain, an easily detected signal, and reduces therequired data storage capacitance value and memory cell size. The lowerbarrier energy increases tunneling current and also advantageouslyreduces the voltage required for writing and erasing the floating gatetransistor memory cells. For example, conventional polysilicon floatinggate transistors typically require complicated and noisy on-chip chargepump circuits to generate the large erasure voltage, which typically farexceeds other voltages required on the integrated circuit. The presentinvention allows the use of lower erasure voltages that are more easilyprovided by simpler on-chip circuits. Reducing the erasure voltage alsolowers the electric fields, minimizing reliability problems that canlead to device failure, and better accommodating downward scaling ofdevice dimensions. Alternatively, the thickness of the gate insulatorcan be increased from the typical thickness of a silicon dioxide gateinsulator to improve reliability or simplify processing, since the lowerbarrier energy allows easier transport of charge across the gateinsulator by Fowler-Nordheim tunneling.

According to another aspect of the invention, the shorter retention timeof data charges on the floating electrode, resulting from the smallerbarrier energy, is accommodated by refreshing the data charges on thefloating electrode. By decreasing the data charge retention time andperiodically refreshing the data, the write and erase operations can beseveral orders of magnitude faster. In this respect, the memory operatessimilar to a memory cell in DRAM, but avoids the process complexity,additional space needed, and other limitations of forming stacked ortrench DRAM capacitors.

The memory cell of the present invention can be made smaller than aconventional DRAM memory cell. Moreover, because the storage capacitorof the present invention is integrally formed as part of the transistor,rather than requiring complex and costly non-CMOS stacked and trenchcapacitor process steps, the memory of the present invention should becheaper to fabricate than DRAM memory cells, and should more easilyscale downward as CMOS technology advances.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like numerals describe substantially similar componentsthroughout the several views.

FIG. 1 is a simplified schematic/block diagram illustrating generallyone embodiment of a memory including reduced barrier energy floatingelectrode memory cells.

FIG. 2 is a cross-sectional view that illustrates generally a floatinggate transistor embodiment of a memory cell provided by the presentinvention.

FIG. 3 is an energy band diagram that illustrates generally conductionband energy levels in a floating gate transistor provided by the presentinvention.

FIG. 4 is a graph comparing barrier energy vs. tunneling distance for aconventional floating gate transistor and one embodiment of a thepresent invention having a lower barrier energy.

FIG. 5 is a graph that illustrates generally the relationship betweenFowler-Nordheim tunneling current density vs. the barrier energy Φ_(GI)at various parameterized values E₁<E₂<E₃ of an electric field.

FIG. 6 illustrates generally how the barrier energy affects the timeneeded to perform write and erase operations by Fowler-Nordheimtunneling for a particular voltage.

FIG. 7 is a graph that illustrates generally charge density vs.write/erase time for three different embodiments of a floating gate FET.

FIG. 8 is a cross-sectional view, similar to FIG. 2, but having a largerarea control gate—floating gate capacitor than the floatinggate—substrate capacitor.

FIG. 9A is a schematic diagram, labeled prior art, that illustratesgenerally a conventional DRAM memory cell.

FIG. 9B is a schematic diagram that illustrates generally one embodimentof a floating gate FET memory cell according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include anysemiconductor-based structure having an exposed surface with which toform the integrated circuit structure of the invention. Wafer andsubstrate are used interchangeably to refer to semiconductor structuresduring processing, and may include other layers that have beenfabricated thereupon. Both wafer and substrate include doped and undopedsemiconductors, epitaxial semiconductor layers supported by a basesemiconductor or insulator, as well as other semiconductor structureswell known to one skilled in the art. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

The present invention discloses a memory cell such as, for example, adynamic electrically alterable programmable read only memory (DEAPROM)cell. The memory cell has a floating electrode, which is defined as anelectrode that is “electrically isolated” from conductors andsemiconductors by an insulator such that charge storage upon and removalfrom the floating electrode depends upon charge conduction through theinsulator. In one embodiment, described below, the floating electrode isa floating gate electrode in a floating gate field-effect transistor,such as used in flash electrically erasable and programmable read onlymemories (EEPROMs). However, a capacitor or any other structure having afloating electrode and adjacent insulator could also be used accordingto the techniques of the present invention described below. According toone aspect of the present invention, a barrier energy between thefloating electrode and the insulator is lower than the barrier energybetween polycrystalline silicon (polysilicon) and silicon dioxide(SiO₂), which is approximately 3.3 eV. According to another aspect ofthe present invention, the shorter retention time of data charges on thefloating electrode, resulting from the smaller barrier energy, isaccommodated by refreshing the data charges on the floating electrode.In this respect, the memory operates similar to a memory cell in adynamic random access memory (DRAM). These and other aspects of thepresent invention are described in more detail below.

FIG. 1 is a simplified schematic/block diagram illustrating generallyone embodiment of a memory 100 according to one aspect of the presentinvention, in which reduced barrier energy floating electrode memorycells are incorporated. Memory 100 is referred to as a dynamicelectrically alterable programmable read only memory (DEAPROM) in thisapplication, but it is understood that memory 100 possesses certaincharacteristics that are similar to DRAMs and flash EEPROMs, asexplained below. Memory 100 includes a memory array 105 of multiplememory cells 110. Row decoder 115 and column decoder 120 decodeaddresses provided on address lines 125 to access the addressed memorycells in memory array 105. Command and control circuitry 130 controlsthe operation of memory 100 in response to control signals received oncontrol lines 135 from a processor 140 or other memory controller duringread, write, refresh, and erase operations. Command and controlcircuitry 130 includes a refresh circuit for periodically refreshing thedata stored on floating gate transistor or other floating electrodememory cells 110. Voltage control 150 provides appropriate voltages tothe memory cells during read, write, refresh, and erase operations.Memory 100, as illustrated in FIG. 1, has been simplified for thepurpose of illustrating the present invention and is not intended to bea complete description. Only the substantial differences between DEAPROMmemory 100 and conventional DRAM and flash EEPROM memories are discussedbelow.

FIG. 2 is a cross-sectional view that illustrates generally, by way ofexample, but not by way of limitation, one floating gate transistorembodiment of a memory cell 110. Other structural arrangements offloating gate transistors are included within the present invention.Also included are any memory cells that incorporate a floating electrode(such as a floating electrode capacitor) having, at an interface betweenthe floating electrode an adjacent insulator, a barrier energy that isless than the barrier energy at a polysilicon-SiO₂ interface. In theembodiment of FIG. 2, memory cell 110 includes a floating gate FET 200,which is illustrated as an n-channel FET, but understood to include ap-channel FET embodiment as well.

FET 200 includes a source 205, a drain 210, a floating gate 215electrode, and a control gate 220 electrode. A gate insulator 225 isinterposed between floating gate 215 and substrate 230. An intergateinsulator 235 is interposed between floating gate 215 and control gate220. In one embodiment, substrate 230 is a bulk semiconductor, such assilicon. In another embodiment, substrate 230 includes a thinsemiconductor surface layer formed on an underlying insulating portion,such as in a semiconductor-on-insulator (SOI) or other thin filmtransistor technology. Source 205 and drain 210 are formed byconventional complementary metal-oxide-semiconductor (CMOS) processingtechniques. Source 205 and drain 210 are separated by a predeterminedlength for forming an inversion channel 240 therebetween.

FIG. 3 is an energy band diagram that illustrates generally theconduction band energy levels in floating gate 215, gate insulator 225,and substrate 230. Electron affinities χ₂₁₅, χ₂₂₅, and χ₂₃₀ describefloating gate 215, gate insulator 225, and substrate 230, respectively,when measured with respect to a vacuum level 300. A barrier energyΦ_(GI), which describes the barrier energy at the interface betweenfloating gate 215 and gate insulator 225, is given by a difference inelectron affinities, as illustrated in Equation 1.Φ_(GI)=χ₂₁₅−χ₂₂₅   (1)A barrier energy Φ_(SG), which describes the barrier energy at theinterface between substrate 230 and gate insulator 225, is given by adifference in electron affinities, as illustrated in Equation 2.Φ_(SG)=χ₂₃₀−χ₂₂₅   (2)Silicon (monocrystalline or polycrystalline Si) has an electron affinityχ₂₁₅≈4.2 eV. Silicon dioxide (SiO₂) has an electron affinity, χ₂₂₅, ofabout 0.9 eV. The resulting barrier energy at a conventional Si-SiO₂interface between a floating gate and a gate insulator is approximatelyequal to 3.3 eV. One aspect of the present invention provides a barrierenergy Φ_(GI) that is less than the 3.3 eV barrier energy of aconventional Si-SiO₂ interface.

According to one aspect of the invention, the interface between floatinggate 215 and gate insulator 225 provides a smaller barrier energy Φ_(GI)than the 3.3 eV barrier energy at an interface between polysilicon andsilicon dioxide, such as by an appropriate selection of the materialcomposition of one or both of floating gate 215 and gate insulator 225.In one embodiment, the smaller barrier energy Φ_(GI) is obtained byforming floating gate 215 from a material having a smaller electronaffinity χ₂₁₅ than polysilicon. In one embodiment, for example,polycrystalline or microcrystalline silicon carbide (SiC) is used as thematerial for forming floating gate 215. In another embodiment, thesmaller barrier energy Φ_(GI) is obtained by forming gate insulator 225from a material having a higher electron affinity χ₂₂₅ than SiO₂. In oneembodiment, for example, amorphous SiC is used as the material forforming gate insulator 225. In yet another embodiment, the smallerbarrier energy Φ_(GI) is obtained by a combination of forming floatinggate 215 from a material having a smaller electron affinity χ₂₁₅ thanpolysilicon and also forming gate insulator 225 from a material having ahigher electron affinity χ₂₂₅ than SiO₂.

The smaller barrier energy Φ_(GI) provides current conduction acrossgate insulator 225 that is easier than for a polysilicon-SiO₂ interface.The present invention includes any mechanism of providing such easiercurrent conduction across gate insulator 225, including, but not limitedto “hot” electron injection, thermionic emission, Schottky emission,Frenkel-Poole emission, and Fowler-Nordheim tunneling. Such techniquesfor transporting charge carriers across an insulator, such as gateinsulator 225, are all enhanced by providing a smaller barrier energyΦ_(GI) according to the techniques of the present invention. Thesetechniques allow increased current conduction, current conduction atlower voltages across gate insulator 225 and lower electric fields ingate insulator 225, shorter data write and erase times, use of a thickerand more reliable gate insulator 225, and other advantages explainedbelow.

FIG. 4 is a graph illustrating generally barrier energy versus tunnelingdistance for a conventional polysilicon-SiO₂ interface having a 3.3 eVbarrier energy. FIG. 4 also illustrates barrier energy versus tunnelingdistance for an interface according to the present invention that has abarrier energy Φ_(GI)≈1.08 eV, which is selected as an illustrativeexample, and not by way of limitation. The smaller barrier energy Φ_(GI)reduces the energy to which the electrons must be excited to be storedon or removed from the floating gate 215, such as by thermal emissionover the barrier. The smaller barrier energy Φ_(GI) also reduces thedistance that electrons have to traverse, such as by Fowler-Nordheimtunneling, to be stored upon or removed from floating gate 215. In FIG.4, “do” represents the tunneling distance of a conventional floatinggate transistor due to the 3.3 eV barrier energy represented by thedashed line “OLD”. The tunneling distance “dn” corresponds to a floatinggate transistor according to the present invention and its smallerbarrier energy, such as Φ_(GI)≈1.08 eV, for example, represented by thedashed line “NEW”. Even a small reduction in the tunneling distanceresults in a large increase in the tunneling probability, as describedbelow, because the tunneling probability is an exponential function ofthe reciprocal of the tunneling distance.

The Fowler-Nordheim tunneling current density in gate insulator 225 isillustrated approximately by Equation 3 below. $\begin{matrix}{J = {{AE}^{2}\quad e^{({- \frac{B}{E}})}}} & (3)\end{matrix}$In Equation 3, J is the current density in units of amperes/cm², E isthe electric field in gate insulator 225 in units of volts/cm and A andB are constants, which are particular to the material of gate insulator225, that depend on the effective electron mass in the gate insulator225 material and on the barrier energy Φ_(GI). The constants A and Bscale with the barrier energy Φ_(GI), as illustrated approximately byEquations 4 and 5. $\begin{matrix}{A\quad\alpha\quad\left( \frac{1}{\Phi_{GI}} \right)} & (4) \\{B\quad\alpha\quad\left( \Phi_{GI} \right)^{\frac{3}{2}}} & (5)\end{matrix}$For a conventional floating gate FET having a 3.3 eV barrier energy atthe interface between the polysilicon floating gate and the SiO₂ gateinsulator, A=5.5×10⁻¹⁶ amperes/Volt² and B=7.07×10⁷ Volts/cm. One aspectof the present invention includes selecting a smaller barrier energyΦ_(GI) such as, by way of example, but not by way of limitation,Φ_(GI)≈1.08 eV. The constants A and B for Φ_(GI)≈1.08 eV can beextrapolated from the constants A and B for the 3.3 eV polysilicon-SiO₂barrier energy using Equations 4 and 5. The barrier energy Φ_(GI)≈1.08eV yields the resulting constants A=1.76×10⁻¹⁵ amperes/Volt² andB=1.24×10⁷ Volts/cm.

FIG. 5 is a graph that illustrates generally the relationship betweenFowler-Nordheim tunneling current density vs. the barrier energy Φ_(GI),such as at various parameterized values E₁<E₂<E₃ of an electric field ingate insulator 225. The tunneling current density increases as electricfield is increased. The tunneling current also increases by orders ofmagnitude as the barrier energy Φ_(GI) is decreased, such as byselecting the materials for floating gate 215 and gate insulator 225 orotherwise reducing the barrier energy Φ_(GI) according to the techniquesof the present invention. In particular, FIG. 5 illustrates a comparisonbetween tunneling current densities at the 3.3 eV barrier energy of aconventional polysilicon-SiO₂ interface and at the illustrative examplebarrier energy Φ_(GI)≈1.08 eV for which constants A and B wereextrapolated above. Reducing the 3.3 eV barrier energy to Φ_(GI)≈1.08 eVincreases the tunneling current density by several orders of magnitude.

FIG. 6 is a conceptual diagram, using rough order of magnitudeestimates, that illustrates generally how the barrier energy affects thetime needed to perform write and erase operations by Fowler-Nordheimtunneling for a particular voltage, such as across gate insulator 225.FIG. 6 also illustrates how the barrier energy affects data chargeretention time, such as on floating gate 215 at a temperature of 250degrees Celsius. Both write and erase time 600 and data charge retentiontime 605 are decreased by orders of magnitude as the barrier energy isdecreased, according to the present invention, from the conventionalpolysilicon-SiO₂ interface barrier energy of 3.3 eV to the illustrativeexample lower barrier energy Φ_(GI)≈1.08 eV for which constants A and Bwere extrapolated above.

The lower barrier energy Φ_(GI) and increased tunneling currentadvantageously provides faster write and erase times. This isparticularly advantageous for “flash” EEPROMs or DEAPROMs in which manyfloating gate transistor memory cells must be erased simultaneously,requiring a longer time to transport the larger quantity of charge. Fora flash EEPROM using a polysilicon floating gate transistor having anunderlying SiO₂ gate insulator 225, the simultaneous erasure of a blockof memory cells requires a time that is on the order of milliseconds.The write and erase time of the floating gate FET 200 is illustratedapproximately by Equation 6. $\begin{matrix}{t = {{\int_{0}^{t}\quad{\mathbb{d}t}} = {\int_{0}^{Q}{\left( \frac{1}{J_{225} - J_{235}} \right)\quad{\mathbb{d}Q}}}}} & (6)\end{matrix}$In Equation 6, t is the write/erase time, J₂₂₅ and J₂₃₅ are therespective tunneling current densities in gate dielectric 225 andintergate dielectric 235, Q is the charge density in Coulombs/cm² onfloating gate 215. Equation 6 is evaluated for a specific voltage oncontrol gate 220 using Equations 7 and 8. $\begin{matrix}{E_{225} = \frac{V_{220}}{\left\lbrack {d_{225} + {d_{235}\quad\left( \frac{\varepsilon_{225}}{\varepsilon_{235}} \right)}} \right\rbrack - \frac{Q}{\left\lbrack {\varepsilon_{225} + {\varepsilon_{235}\left( \frac{d_{225}}{d_{235}} \right)}} \right\rbrack}}} & (7) \\{E_{235} = \frac{V_{220}}{\left\lbrack {d_{235} + {d_{225}\quad\left( \frac{\varepsilon_{235}}{\varepsilon_{225}} \right)}} \right\rbrack + \frac{Q}{\left\lbrack {\varepsilon_{235} + {\varepsilon_{225}\left( \frac{d_{235}}{d_{225}} \right)}} \right\rbrack}}} & (8)\end{matrix}$In Equations 7 and 8, V₂₂₀ is the voltage on control gate 220, E₂₂₅ andE₂₃₅ are the respective electric fields in gate insulator 225 andintergate insulator 235, d₂₂₅ and d₂₃₅ are the respective thicknesses ofgate insulator 225 and intergate insulator 235, and ε₂₂₅ and ε₂₃₅ arethe respective permittivities of gate insulator 225 and intergateinsulator 235.

FIG. 7 is a graph that illustrates generally charge density vs.write/erase time for three different embodiments of the floating gateFET 200, each of which have a polysilicon floating gate 215, by way ofillustrative example. Line 700 illustrates generally, by way of example,but not by way of limitation, the charge density vs. write/erase timeobtained for a floating gate FET 200 having a 100 Å SiO₂ gate insulator225 and a 150 Å SiO₂ (or thinner oxynitride equivalent capacitance)intergate insulator 235.

Line 705 is similar to line 700 in all respects except that line 705illustrates a floating gate FET 200 in which gate insulator 225comprises a material having a higher electron affinity χ₂₂₅ than SiO₂,thereby providing a lower barrier energy Φ_(GI) at the interface betweenpolysilicon floating gate 215 and gate insulator 225. The increasedtunneling current results in shorter write/erase times than thoseillustrated by line 700.

Line 710 is similar to line 705 in all respects except that line 710illustrates a w floating gate FET 200 in which gate insulator 225 has alower barrier energy Φ_(GI) than for line 705, or intergate insulator235 has a higher permittivity ε₂₃₅ than for line 705, or control gate220 has a larger area than floating gate 215, such as illustrated by wayof example by the floating gate FET 800 in the cross-sectional view ofFIG. 8. As seen in FIG. 8, the area of a capacitor formed by the controlgate 220, the floating gate 215, and the intergate insulator 235 islarger than the area of a capacitor formed by the floating gate 215, thegate insulator 225, and the inversion channel 240 underlying gateinsulator 225. Alternatively, or in combination with the techniquesillustrated in FIG. 8, the intergate insulator 235 can have a higherpermittivity than the permittivity of silicon dioxide.

As illustrated in FIG. 7, the barrier energy Φ_(GI) can be selected toreduce the write/erase time. In one embodiment, by way of example, butnot by way of limitation, the barrier energy Φ_(GI) is selected toobtain a write/erase time of less than or equal to 1 second, asillustrated in FIG. 7. In another embodiment, by way of example, but notby way of limitation, the barrier energy Φ_(GI) is selected to obtain awrite/erase time of less than or equal to 1 millisecond, as illustratedin FIG. 7. Other values of write/erase time can also be obtained byselecting the appropriate value of the barrier energy Φ_(GI).

The lower barrier energy Φ_(GI) and increased tunneling current alsoadvantageously reduces the voltage required for writing and erasing thefloating gate transistor memory cells 110. For example, conventionalpolysilicon floating gate transistors typically require complicated andnoisy on-chip charge pump circuits to generate the large erasurevoltage, which typically far exceeds other voltages required on theintegrated circuit. The present invention allows the use of lowererasure voltages that are more easily provided by simpler on-chipcircuits. Reducing the erasure voltage also lowers the electric fields,minimizing reliability problems that can lead to device failure, andbetter accommodating downward scaling of device dimensions. In oneembodiment, the barrier energy Φ_(GI) is selected, as described above,to obtain an erase voltage of less than the 12 Volts required by typicalEEPROM memory cells.

Alternatively, the thickness of the gate insulator 225 can be increasedfrom the typical thickness of a silicon dioxide gate insulator toimprove reliability or simplify processing, since the lower barrierenergy Φ_(GI) allows easier transport of charge across the gateinsulator 225 by Fowler-Nordheim tunneling.

The lower barrier energy Φ_(GI) also decreases the data charge retentiontime of the charge stored on the floating gate 215, such as fromincreased thermal excitation of stored charge over the lower barrierΦ_(GI). However, conventional polysilicon floating gates and adjacentSiO₂ insulators (e.g., 90 Å thick) have a data charge retention timeestimated in the millions of years at a temperature of 85 degrees C.,and estimated in the 1000 hour range even at extremely high temperaturessuch as 250 degrees C. Since such long data charge retention times arelonger than what is realistically needed, a shorter data chargeretention time can be accommodated in order to obtain the benefits ofthe smaller barrier energy Φ_(GI). In one embodiment of the presentinvention, by way of example, but not by way of limitation, the barrierenergy Φ_(GI) is lowered to Φ_(GI)≈1.08 eV by appropriately selectingthe composition of the materials of floating gate 215 and gate insulator225, as described below. As a result, an estimated data charge retentiontime of approximately 40 seconds at a high temperature, such as 250degrees C., is obtained.

According to one aspect of the present invention, the data stored on theDEAPROM floating gate memory cell 110 is periodically refreshed at aninterval that is shorter than the data charge retention time. In oneembodiment, for example, the data is refreshed every few seconds, suchas for an embodiment having a high temperature retention time ofapproximately 40 seconds for Φ_(GI)≈1.08 eV. The exact refresh rate canbe experimentally determined and tailored to a particular process offabricating the DEAPROM. By decreasing the data charge retention timeand periodically refreshing the data, the write and erase operations canbe several orders of magnitude faster, as described above with respectto FIG. 7.

FIGS. 9A and 9B are schematic diagrams that respectively illustrategenerally a conventional DRAM memory cell and the present invention'sfloating gate FET 200 embodiment of memory cell 110. In FIG. 9A, theDRAM memory cell includes an access FET 900 and stacked or trenchstorage capacitor 905. Data is stored as charge on storage capacitor 905by providing a control voltage on control line 910 to activate FET 900for conducting charge. Data line 915 provides a write voltage to conductcharge across FET 900 for storage on storage capacitor 905. Data is readby providing a control voltage on control line 910 to activate FET 900for conducting charge from storage capacitor 905, thereby incrementallychanging a preinitialized voltage on data line 915. The resulting smallchange in voltage on data line 915 must be amplified by a senseamplifier for detection. Thus, the DRAM memory cell of FIG. 9Ainherently provides only a small data signal. The small data signal isdifficult to detect.

In FIG. 9B, the DEAPROM memory cell 110 according to the presentinvention includes floating gate FET 200, having source 205 coupled to aground voltage or other reference potential. Data is stored as charge onfloating gate 215 by providing a control voltage on control line 920 anda write voltage on data line 925 for hot electron injection orFowler-Nordheim tunneling. This is similar to conventional EEPROMtechniques, but advantageously uses the reduced voltages and/or ashorter write time of the present invention.

The DEAPROM memory cell 110 can be smaller than the DRAM memory cell ofFIG. 9A, allowing higher density data storage. The leakage of chargefrom floating gate 215 can be made less than the reverse-bias junctionleakage from storage capacitor 905 of the DRAM memory cell by tailoringthe barrier energy Φ_(GI) according to the techniques of the presentinvention. Also, the DEAPROM memory cell advantageously uses the largetransconductance gain of the floating gate FET 200. The conventionalDRAM memory cell of FIG. 9A provides no such gain; it is read bydirectly transferring the data charge from storage capacitor 905. Bycontrast, the DEAPROM memory cell 110 is read by placing a read voltageon control line 920, and detecting the current conducted through FET200, such as at data line 925. The current conducted through FET 200changes significantly in the presence or absence of charge stored onfloating gate 215. Thus, the present invention advantageously providesan large data signal that is easy to detect, unlike the small datasignal provided by the conventional DRAM memory cell of FIG. 9A.

For example, the current for floating gate FET 200 operating in thesaturation region can be approximated by Equation 9. $\begin{matrix}{I_{DS} = {\frac{1}{2}\quad\mu\quad C_{o}\quad\left( \frac{W}{L} \right)\quad\left( {V_{G} - V_{T}} \right)^{2}}} & (9)\end{matrix}$In Equation 9, I_(DS) is the current between drain 210 and source 205,C_(o) is the capacitance per unit area of the gate insulator 225, W/L isthe width/length aspect ratio of FET 200, V_(G) is the gate voltageapplied to control gate 220, and V_(T) is the turn-on threshold voltageof FET 200.

For an illustrative example, but not by way of limitation, aminimum-sized FET having W/L=1, can yield a transconductance gain ofapproximately 71 μA/Volt for a typical process. In this illustrativeexample, sufficient charge is stored on floating gate 215 to change theeffective threshold voltage V_(T) by approximately 1.4 Volts, therebychanging the current I_(DS) by approximately 100 microamperes. Thissignificant change in current can easily be detected, such as bysampling or integrating over a time period of approximately 10nanoseconds, for example, to obtain a detected data charge signal of1000 fC. Thus, the DEAPROM memory cell 110 is capable of yielding adetected data charge signal that is approximately an order of magnitudelarger than the typical 30 fC to 100 fC data charges typically stored onDRAM stacked or trench capacitors. Since DEAPROM memory cell 110requires a smaller capacitance value than a conventional DRAM memorycell, DEAPROM memory cell 110 can be made smaller than a conventionalDRAM memory cell. Moreover, because the CMOS-compatible DEAPROM storagecapacitor is integrally formed as part of the transistor, rather thanrequiring complex and costly non-CMOS stacked and trench capacitorprocess steps, the DEAPROM memory of the present invention should becheaper to fabricate than DRAM memory cells, and should more easilyscale downward as CMOS technology advances.

Amorphous SiC Gate Insulator Embodiment

In one embodiment, the present invention provides a DEAPROM having astorage element including a gate insulator 225 that includes anamorphous silicon carbide (a-SiC). For example, one embodiment of amemory storage element having an a-SiC gate insulator 225 is describedin Forbes et al. U.S. patent application Ser. No. 08/903,453 entitledCARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS, filed on thesame day as the present patent application, and which disclosure isherein incorporated by reference. The a-SiC inclusive gate insulator 225provides a higher electron affinity χ₂₂₅ than the approximately 0.9 eVelectron affinity of SiO₂. For example, but not by way of limitation,the a-SiC inclusive gate insulator 225 can provide an electron affinityχ₂₂₅≈3.24 eV.

An a-SiC inclusive gate insulator 225 can also be formed using othertechniques. For example, in one embodiment gate insulator 225 includes ahydrogenated a-SiC material synthesized by ion-implantation of C₂H₂ intoa silicon substrate 230. In another embodiment, gate insulator 225includes an a-SiC film that is deposited by laser ablation at roomtemperature using a pulsed laser in an ultrahigh vacuum or nitrogenenvironment. In another embodiment, gate insulator 225 includes an a-SiCfilm that is formed by low-energy ion-beam assisted deposition tominimize structural defects and provide better electricalcharacteristics in the semiconductor substrate 230. The ion beam can begenerated by electron cyclotron resonance from an ultra high purityargon (Ar) plasma.

In another embodiment, gate insulator 225 includes an a-SiC film that issynthesized at low temperature by ion beam sputtering in a reactive gasenvironment with concurrent ion irradiation. According to one technique,more than one ion beam, such as an Ar ion beam, are used. A first Ar ionbeam is directed at a Si target material to provide a Si flux forforming SiC gate insulator 225. A second Ar ion beam is directed at agraphite target to provide a C flux for forming SiC gate insulator 225.The resulting a-SiC gate insulator 225 is formed by sputtering onsubstrate 230. In another embodiment, gate insulator 225 includes an SiCfilm that is deposited on substrate 230 by DC magnetron sputtering atroom temperature using a conductive, dense ceramic target. In anotherembodiment, gate insulator 225 includes a thin a-Si_(1-x)C_(x):H filmthat is formed by HF plasma ion sputtering of a fused SiC target in anAr-H atmosphere. In another embodiment, radio frequency (RF) sputteringis used to produce a-SiC films. Bandgaps of a-Si, a-SiC, a-Si:H, anda-SiC:H have been found to be 1.22 eV, 1.52 eV, 1.87 eV, and 2.2 eVrespectively.

In another embodiment, gate insulator 225 is formed by chemical vapordeposition (CVD) and includes an a-SiC material. According to onetechnique, gate insulator 225 includes a-Si_(1-x)C_(x):H deposited byplasma enhanced chemical vapor deposition (PECVD). According to anothertechnique, mixed gases of silane and methane can be used to forma-Si_(1-x)C_(x):H gate insulator 225. For example, the source gas caninclude silane in methane with additional dilution in hydrogen. Inanother embodiment, gate insulator 225 includes a clean a-Si_(1-x)C_(x)material formed by hot-filament assisted CVD. In another embodiment,gate insulator 225 includes a-SiC formed on a crystalline Si substrate230 by inductively coupled plasma CVD, such as at 450 degrees Celsius,which can yield a-SiC rather than epitaxially grown polycrystalline ormicrocrystalline SiC. The resulting a-SiC inclusive gate insulator 225can provide an electron affinity χ₂₂₅≈3.24 eV, which is significantlylarger than the 0.9 eV electron affinity obtainable from a conventionalSiO₂ gate insulator.

Gate insulator 225 can be etched by RF plasma etching using CF₄O₂ inSF₆O₂. Self-aligned source 205 and drain 210 can then be formed usingconventional techniques for forming a FET 200 having a floating(electrically isolated) gate 215, or in an alternate embodiment, anelectrically interconnected (driven) gate.

SiC Gate Material Embodiment

In one embodiment, the present invention provides a DEAPROM having amemory cell 110 that includes a FET 200 having an at least partiallycrystalline (e.g., monocrystalline, polycrystalline, microcrystalline,nanocrystalline, or combination thereof) SiC floating gate 215. Forexample, one embodiment of a memory cell 110 that includes a memorystorage element having a polycrystalline or microcrystalline SiCfloating gate 215 is described in Forbes et al. U.S. patent applicationSer. No. 08/903,486 entitled SILICON CARBIDE GATE TRANSISTOR ANDFABRICATION PROCESS, filed on the same day as the present patentapplication, and which disclosure is herein incorporated by reference.The SiC floating gate 215 provides a lower electron affinity χ₂₁₅≈3.7 to3.8 eV and smaller resulting barrier energy Φ_(GI) than a polysilicongate material having an electron affinity χ₂₁₅≈4.2 eV. For example,using a SiO₂ gate insulator 225, a barrier energy Φ_(GI)≈2.6 to 2.7 eVis obtained using an SiC floating gate 215, as compared to a barrierenergy Φ_(GI)≈3.3 eV for a conventional polysilicon floating gatematerial at an interface with an SiO₂ gate insulator 225.

According to one aspect of the invention, floating gate 215 is formedfrom a silicon carbide compound Si_(1-x)C_(x), in which the materialcomposition x is varied. One embodiment of a memory storage elementhaving a variable SiC composition floating gate 215 is described inForbes et al. U.S. patent application Ser. No. 08/903,452 entitledTRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE AND METHODS OFFABRICATION AND USE, filed on the same day as the present patentapplication, and which disclosure is herein incorporated by reference.For example, but not by way of limitation, an SiC composition of about0.75<x<1.0 yields an electron affinity of approximately between 1.7eV<χ₂₁₅<−0.4 eV. For an SiO₂ gate insulator 225, a barrier 0.8eV<Φ_(GI)<−1.3 eV is obtained. In one such embodiment, floating gate FET200 provides a data charge retention time on the order of seconds.

In one embodiment, floating gate 215 is formed by CVD of polycrystallineor microcrystalline SiC, which can be either in situ conductively dopedduring deposition, or conductively doped during a subsequention-implantation step. According to one aspect of the invention, forexample, floating gate 215 is formed of an SiC film that is depositedusing low-pressure chemical vapor deposition (LPCVD). The LPCVD processuses either a hot-wall reactor or a cold-wall reactor with a reactivegas, such as a mixture of Si(CH₃)₄ and Ar. In other embodiments,floating gate 215 is formed of an SiC film that is deposited using othertechniques such as, for example, enhanced CVD techniques known to thoseskilled in the art including low pressure rapid thermal chemical vapordeposition (LP-RTCVD), or by decomposition of hexamethyl disalene usingArF excimer laser irradiation, or by low temperature molecular beamepitaxy (MBE). Other examples of forming SiC film floating gate 215include reactive magnetron sputtering, DC plasma discharge, ion-beamassisted deposition, ion-beam synthesis of amorphous SiC films, lasercrystallization of amorphous SiC, laser reactive ablation deposition,and epitaxial growth by vacuum anneal. The conductivity of the SiC filmof floating gate 215 can be changed by ion implantation duringsubsequent process steps, such as during the self-aligned formation ofsource/drain regions for the n-channel and p-channel FETs.

In one embodiment, patterning and etching the SiC film, together withthe underlying gate insulator 225, forms the resulting individual SiCfloating gates 215. The SiC film is patterned using standard techniquesand is etched using plasma etching, reactive ion etching (RIE) or acombination of these or other suitable methods. For example, the SiCfilm can be etched by RIE in a distributed cyclotron resonance reactorusing a SF₆/O₂ gas mixture using SiO₂ as a mask with a selectivity of6.5. Alternatively, the SiC film can be etched by RIE using the mixtureSF₆ and O₂ and F₂/Ar/O₂. The etch rate of the SiC film can besignificantly increased by using magnetron enhanced RIE. Self-alignedsource 205 and drain 210 regions can then be formed using conventionaltechniques for forming a FET 200 having a floating (electricallyisolated) gate 215, or in an alternate embodiment, an electricallyinterconnected (driven) gate.

SiOC Gate Material Embodiment

In one embodiment, the present invention provides a DEAPROM having amemory cell 110 that includes a FET 200 having an at least partiallycrystalline (e.g., monocrystalline, polycrystalline, microcrystalline,or nanocrystalline) silicon oxycarbide (SiOC) floating gate 215. Forexample, one embodiment of a memory cell 110 that includes a storageelement having a polycrystalline or microcrystalline SiOC floating gate215 is described in Forbes et al. U.S. patent application Ser. No.08/902,132 entitled TRANSISTOR WITH SILICON OXYCARBIDE GATE AND METHODSOF FABRICATION AND USE, filed on the same day as the present patentapplication, and which disclosure is herein incorporated by reference.

In one embodiment, a material composition w of the SiO_((2-2w))C_(w)floating gate 215 is selected such that floating gate 215 provides alower electron affinity approximately between 0.9 eV<χ₂₁₅<3.7 eV andsmaller resulting barrier energy Φ_(GI) than a polysilicon gate materialhaving an electron affinity χ₂₁₅≈4.2 eV. For example, using a SiO₂ gateinsulator 225, a barrier energy approximately between 0 eV<Φ_(GI)<2.8 eVis obtained for an SiOC floating gate 215 as the SiOC composition wvaries between w≈1 (i.e., approximately SiC) and w≈0 (i.e.,approximately SiO₂). By contrast, a conventional polysilicon floatinggate material provides a barrier energy Φ_(GI)≈3.3 eV at an interfacewith an SiO₂ gate insulator 225.

In one embodiment floating gate 215 is formed of a monocrystalline,polycrystalline, microcrystalline, or nanocrystalline, SiOC thin filmthat is CVD deposited, such as by a Two Consecutive Decomposition andDeposition Chamber (TCDDC) system.

In other embodiments, the SiOC film is deposited using other techniquessuch as, for example, low pressure chemical vapor deposition (LPCVD), orenhanced CVD techniques known to those skilled in the art including lowpressure rapid thermal chemical vapor deposition (LP-RTCVD). Theconductivity of the SiOC film floating gate 215 can be changed by ionimplantation during subsequent process steps, such as during theself-aligned formation of source/drain regions for the n-channel andp-channel FETs. The SiOC film can be patterned and etched, together withthe underlying gate insulator 225, such as by using plasma etching,reactive ion etching (RIE) or a combination of these or other suitablemethods. The etch rate of SiOC film can be significantly increased byusing magnetron enhanced RIE.

GaN and GaAlN Gate Material Embodiments

In one embodiment, the present invention provides a DEAPROM having amemory cell 110 including a FET 200 having an at least partiallycrystalline (e.g., monocrystalline, polycrystalline, microcrystalline,nanocrystalline, or combination thereof) gallium nitride (GaN) orgallium aluminum nitride (GaAlN) floating gate 215. For example, oneembodiment of a memory storage element having a GaN or GaAlN floatinggate 215 is described in Forbes et al. U.S. patent application Ser. No.08/902,098 entitled DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE ORGALLIUM ALUMINUM NITRIDE GATE, filed on the same day as the presentpatent application, and which disclosure is herein incorporated byreference.

In one embodiment, a composition v of a polycrystalline Ga_(1-v)Al_(v)Nfloating gate 215 is selected approximately between 0<v<1 to obtain adesired barrier energy, as described below. The GaAlN floating gate 215provides a lower electron affinity than polysilicon. The GaAlN floatinggate 215 electron affinity can be approximately between 0.6 eV<χ₂₁₅<2.7eV as the GaAlN composition variable v is decreased from 1 to 0. As aresult, the GaAlN floating gate 215 provides a smaller resulting barrierenergy Φ_(GI) than a polysilicon gate material having an electronaffinity χ₂₁₅≈4.2 eV. For example, using a SiO₂ gate insulator 225, abarrier energy approximately between −0.3 eV<Φ_(GI)<1.8 eV is obtainedusing an GaAlN floating gate 215 as the GaAlN composition v variesbetween v≈1 (i.e., approximately AlN) and v≈0 (i.e., approximately GaN).By contrast, a conventional polysilicon floating gate material providesa barrier energy Φ_(GI)≈3.3 eV at an interface with an SiO₂ gateinsulator 225.

In one embodiment, substrate 230 is bulk silicon, although other bulksemiconductor and semiconductor-on-insulator (SOI) materials could alsobe used for substrate 230 such as, for example, sapphire, galliumarsenide (GaAs), GaN, AlN, and diamond. In one embodiment, gateinsulator 225 is SiO₂, although other dielectric materials could also beused for gate insulator 225, as described above, such as amorphousinsulating GaN (a-GaN), and amorphous insulating AlN (a-AlN). The FET200 using a GaAlN floating gate 215 has mobility and turn-on thresholdvoltage (V_(T)) magnitude parameters that are advantageously influencedless by charge at SiO₂-GaAlN interface surface states than at aconventional SiO₂-polysilicon interface.

In one embodiment floating gate 215 is formed of a polycrystalline,microcrystalline, or nanocrystalline, GaN thin film that is CVDdeposited on a thin (e.g., 500 Å thick) AlN buffer layer, such as bymetal organic chemical vapor deposition (MOCVD), which advantageouslyyields improved crystal quality and reduced microscopic fluctuation ofcrystallite orientation.

In one embodiment, floating gate 215 is formed from a GaN film grown ina horizontal reactor operating at atmospheric pressure. Trimethylgallium (TMG), trimethylaluminum (TMA), and ammonia (NH₃) are used assource gases, and hydrogen (H₂) is used as a carrier gas. The TMG, TMA,and NH₃ are mixed just before the reactor, and the mixture is fed athigh velocity (e.g., 110 cm/s) to a slanted substrate 230 through adelivery tube. The desired GaAlN composition v is obtained bycontrolling the concentration ratio of TMG to TMA. In one embodiment, a500 Å AlN buffer layer is obtained by growth at 600 degrees Celsius at adeposition rate of 100 Å/minute for approximately 5 minutes, then aepitaxial crystalline or polycrystalline layer of GaN is deposited at1000 degrees Celsius.

In another embodiment plasma-enhanced molecular beam epitaxy (PEMBE) isused to form a GaN or GaAlN floating gate 215, for example, by usingelectron cyclotron resonance (ECR) plasma during molecular beam epitaxy(MBE). The background pressure in the MBE chamber is typically less than10⁻¹⁰ torr. Ga flux (e.g., 99.99999% pure) is supplied by a conventionalKnudsen effusion cell. The semiconductor substrates 230 are heated to atemperature of approximately 850 degrees Celsius, and exposed to anitrogen plasma (e.g., 35 Watt plasma power level) to clean the surfaceof the substrate 230 and form a thin AlN layer thereupon. Thetemperature is then lowered to approximately 550 degrees Celsius forgrowth of a thin (e.g., 300 Å) GaN buffer layer (e.g., using 20 Wattplasma power level for growth in a low active nitrogen overpressureenvironment). The temperature is then increased, such as toapproximately 800 degrees Celsius, to form the remainder of the GaN orGaAlN film forming floating gate 225, such as at a deposition rate ofapproximately 0.22 microns/hour.

CONCLUSION

Each memory cell described herein has a floating electrode, such as afloating gate electrode in a floating gate field-effect electrode andthe insulator is lower than the barrier energy between polysilicon andSiO₂, which is approximately 3.3 eV. Each memory cell also provideslarge transconductance gain, which provides a more easily detectedsignal and reduces the required data storage capacitance value.According to another aspect of the invention, the shorter retention timeof data charges on the floating electrode, resulting from the smallerbarrier energy, is accommodated by refreshing the data charges on thefloating electrode. By decreasing the data charge retention time andperiodically refreshing the data, the write and erase operations can beseveral orders of magnitude faster. In this respect, each memoryoperates similar to a memory cell in DRAM, but avoids the processcomplexity, additional space needed, and other limitations of formingstacked or trench DRAM capacitors.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that theabove-described embodiments can be used in combination, and anyarrangement which is calculated to achieve the same purpose may besubstituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A transistor comprising: a source region; a drain region; a channelregion between the source region and the drain region; a floating gateseparated from the channel region by an insulator, the floating gatebeing conductively doped and comprising a material that has a smallerelectron affinity than polycrystalline silicon and a barrier energybetween the floating gate and the insulator being less thanapproximately 3.3 eV, the insulator having a larger electron affinitythan silicon dioxide; a control electrode, separated from the floatinggate by an intergate dielectric; and wherein the intergate dielectrichas a permittivity that is higher than a permittivity of silicondioxide, wherein: the insulator comprises a material that has a largerelectron affinity than silicon dioxide; the floating gate comprisespolycrystalline or microcrystalline silicon carbide; the barrier energyis less than approximately 2.0 eV; and an area of a capacitor formed bythe control electrode, the floating gate, and the intergate dielectricis larger than an area of a capacitor formed by the floating gate, theinsulator, and the channel region.
 2. A transistor comprising: a sourceregion; a drain region; a channel region between the source region andthe drain region; a floating gate separated from the channel region byan insulator, the floating gate comprising a material that has anelectron affinity less than or equal to 2.7 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.7 eV; a control electrode, separated from the floatinggate by an intergate dielectric; and wherein the intergate dielectrichas a permittivity that is higher than a permittivity of silicondioxide.
 3. The transistor of claim 2 wherein: an area of a capacitorformed by the control electrode, the floating gate, and the intergatedielectric is larger than an area of a capacitor formed by the floatinggate, the insulator, and the channel region.
 4. A transistor comprising:a source region; a drain region; a channel region between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate being conductively doped andcomprising a material that has an electron affinity less than or equalto 2.7 eV and a barrier energy between the floating gate and theinsulator being less than approximately 1.8 eV, the insulator having alarger electron affinity than silicon dioxide; a control electrode,separated from the floating gate by an intergate dielectric; and whereinthe intergate dielectric has a permittivity that is higher than apermittivity of silicon dioxide.
 5. The memory cell of claim 4, whereinmaterials comprising at least one of the storage electrode and theinsulator are selected to have an electron affinity causing the barrierenergy to be selected at less than approximately 1.2 eV.
 6. Thetransistor of claim 4, wherein the barrier energy is selected to obtaina data charge retention time of the transistor that is adapted fordynamic refreshing of charge stored on the floating gate.
 7. Thetransistor of claim 4, wherein the floating gate is isolated fromconductors and semiconductors.
 8. The transistor of claim 4, wherein thefloating gate is capacitively separated from the channel region forproviding transconductance gain.
 9. A memory cell comprising: a storageelectrode comprising a material that has an electron affinity less thanor equal to 2.7 eV to store charge; an insulator adjacent to the storageelectrode, wherein a barrier energy between the insulator and thestorage electrode is less than approximately 1.8 eV, the insulatorhaving a larger electron affinity than silicon dioxide; a controlelectrode separated from the storage electrode by an intergatedielectric; and wherein the intergate dielectric has a permittivity thatis higher than a permittivity of silicon dioxide.
 10. The memory cell ofclaim 2, wherein materials comprising at least one of the storageelectrode and the insulator are selected to have an electron affinitycausing the barrier energy to be selected at less than approximately 0.8eV.
 11. The memory cell of claim 2, wherein the barrier energy isselected to obtain a desired data charge retention time of less than orequal to approximately 40 seconds at 250 degrees Celsius.
 12. The memorycell of claim 2, wherein the barrier energy is selected to obtain adesired erase time of less than approximately 1 second.
 13. The memorycell of claim 2, wherein the barrier energy is selected to obtain adesired erase voltage of less than approximately 12 Volts.
 14. Thememory cell of claim 2, wherein the barrier energy is less thanapproximately 1.0 eV.
 15. The memory cell of claim 2, wherein thestorage electrode is isolated from conductors and semiconductors. 16.The memory cell of claim 2, wherein the storage electrode istransconductively capacitively coupled to a channel.
 17. The memory cellof claim 9, further comprising: a source region in a substrate; a drainregion in the substrate; a channel region in the substrate between thesource region and the drain region; and wherein: the storage electrodecomprises Si_(1-x)C_(x); the insulator is between the storage electrodeand the channel region, and the barrier energy is less thanapproximately 0.6 eV; and an area of a capacitor formed by the controlelectrode, the storage electrode, and the intergate dielectric is largerthan an area of a capacitor formed by the storage electrode, theinsulator, and the channel region.
 18. A memory device comprising: aplurality of memory cells, wherein each memory cell includes atransistor comprising: a source region; a drain region; a channel regionbetween the source and drain regions; a floating gate separated from thechannel region by an insulator, the floating gate being conductivelydoped and comprising a material that has an electron affinity less thanor equal to 2.7 eV and a barrier energy between the floating gate andthe insulator being less than approximately 1.8 eV, the insulator havinga larger electron affinity than silicon dioxide; and a control gatelocated adjacent to the floating gate and separated therefrom by anintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 19. The memory device of claim 18wherein the barrier energy is selected to obtain a data charge retentiontime for each transistor that is adapted for dynamic refreshing ofcharge stored on the floating gate.
 20. The memory device of claim 18wherein the floating gate of each transistor is isolated from conductorsand semiconductors.
 21. The memory device of claim 18 wherein thefloating gate of each transistor is capacitively separated from thechannel region for providing transconductance gain.
 22. A memory devicecomprising: a plurality of memory cells, wherein each memory cellincludes a transistor comprising: a source region; a drain region; achannel region between the source and drain regions; a floating gateseparated from the channel region by an insulator, the floating gatebeing conductively doped and comprising a material that has a smallerelectron affinity than polycrystalline silicon and a barrier energybetween the floating gate and the insulator being less thanapproximately 3.3 eV, the insulator having a larger electron affinitythan silicon dioxide; and a control gate located adjacent to thefloating gate and separated therefrom by an intergate dielectric havinga permittivity that is higher than a permittivity of silicon dioxide,wherein: the floating gate comprises polycrystalline or microcrystallinesilicon carbide; the barrier energy is less than approximately 2.0 eV;and an area of a capacitor formed by the control gate, the floatinggate, and the intergate dielectric is larger than an area of a capacitorformed by the floating gate, the insulator, and the channel region ofeach transistor.
 23. A transistor comprising: a source region in asubstrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; an insulatorcomprising a material that has a larger electron affinity than silicondioxide; a floating gate separated from the channel region by theinsulator, the floating gate comprising a material that has an electronaffinity less than 2.7 eV and a barrier energy between the floating gateand the insulator being less than approximately 1.7 eV; and a controlgate, separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 24. A transistor comprising: a sourceregion in a substrate; a drain region in the substrate; a channel regionin the substrate between the source region and the drain region; aninsulator comprising a material that has a larger electron affinity thansilicon dioxide; a floating gate separated from the channel region bythe insulator, the floating gate comprising a material that has asmaller electron affinity than polycrystalline silicon and a barrierenergy between the floating gate and the insulator being less thanapproximately 3.3 eV; and a control gate, separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide,wherein: the insulator comprises amorphous silicon carbide; the floatinggate comprises polycrystalline or microcrystalline silicon carbide; andthe barrier energy is less than approximately 2.0 eV.
 25. A transistorcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate comprising a material that has anelectron affinity less than 2.7 eV and a barrier energy between thefloating gate and the insulator being less than approximately 1.8 eV,the insulator having a larger electron affinity than silicon dioxide;and a control gate, separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide.
 26. A transistorcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate comprising a material that has asmaller electron affinity than polycrystalline silicon and a barrierenergy between the floating gate and the insulator being less thanapproximately 3.3 eV, the insulator having a larger electron affinitythan silicon dioxide; and a control gate, separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide,wherein: the floating gate comprises polycrystalline or microcrystallinesilicon carbide; an area of a capacitor formed by the control gate, thefloating gate, and the intergate dielectric is larger than an area of acapacitor formed by the floating gate, the insulator, and the channelregion; and the barrier energy is less than approximately 2.0 eV.
 27. Atransistor comprising: a source region in a substrate; a drain region inthe substrate; a channel region in the substrate between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate comprising a material that hasan electron affinity less than or equal to 2.7 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.8 eV, the insulator having a larger electron affinitythan silicon dioxide; a control gate, separated from the floating gateby an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide; andwherein an area of a capacitor formed by the control gate, the floatinggate, and the intergate dielectric is larger than an area of a capacitorformed by the floating gate, the insulator, and the channel region. 28.A transistor comprising: a source region in a substrate; a drain regionin the substrate; a channel region in the substrate between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate comprising a material that hasa smaller electron affinity less than polycrystalline silicon and abarrier energy between the floating gate and the insulator being lessthan approximately 3.3 eV, the insulator having a larger electronaffinity than silicon dioxide; a control gate, separated from thefloating gate by an intergate dielectric, the intergate dielectrichaving a permittivity that is higher than a permittivity of silicondioxide; and wherein an area of a capacitor formed by the control gate,the floating gate, and the intergate dielectric is larger than an areaof a capacitor formed by the floating gate, the insulator, and thechannel region, wherein: the floating gate comprises polycrystalline ormicrocrystalline silicon carbide; and the barrier energy is less thanapproximately 2.0 eV.
 29. A transistor comprising: a source region in asubstrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; an insulatorcomprising a material that has a larger electron affinity than silicondioxide; a floating gate separated from the channel region by theinsulator, the floating gate comprising a material that has an electronaffinity less than or equal to 2.7 eV and a barrier energy between thefloating gate and the insulator being less than approximately 1.8 eV; acontrol gate separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide; and an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region.
 30. A transistorcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; an insulator comprising a material that has alarger electron affinity than silicon dioxide; a floating gate separatedfrom the channel region by the insulator, the floating gate comprising amaterial that has a smaller electron affinity than polycrystallinesilicon and a barrier energy between the floating gate and the insulatorbeing less than approximately 3.3 eV; a control gate separated from thefloating gate by an intergate dielectric, the intergate dielectrichaving a permittivity that is higher than a permittivity of silicondioxide; and an area of a capacitor formed by the control gate, thefloating gate, and the intergate dielectric is larger than an area of acapacitor formed by the floating gate, the insulator, and the channelregion, wherein: the insulator comprises amorphous silicon carbide; thebarrier energy is less than approximately 2.0 eV; and the floating gatecomprises polycrystalline or microcrystalline silicon carbide.
 31. Atransistor comprising: a source region in a substrate; a drain region inthe substrate; a channel region in the substrate between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate comprising a material that hasan electron affinity less than or equal to 2.5 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.6 eV, the insulator having a larger electron affinitythan silicon dioxide; and a control gate separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide. 32.The transistor of claim 31 wherein: the floating gate comprisespolycrystalline or microcrystalline silicon carbide; and an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region.
 33. A transistorcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate comprising a material that has anelectron affinity less than or equal to 2.5 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.6 eV; a control gate separated from the floating gate byan intergate dielectric, the intergate dielectric having a permittivitythat is higher than a permittivity of silicon dioxide; and wherein anarea of a capacitor formed by the control gate, the floating gate, andthe intergate dielectric is larger than an area of a capacitor formed bythe floating gate, the insulator, and the channel region.
 34. Atransistor comprising: a source region in a substrate; a drain region inthe substrate; a channel region in the substrate between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate comprising a material that hasa smaller electron affinity than polycrystalline silicon and a barrierenergy between the floating gate and the insulator being less thanapproximately 2.0 eV; a control gate separated from the floating gate byan intergate dielectric, the intergate dielectric having a permittivitythat is higher than a permittivity of silicon dioxide; and wherein anarea of a capacitor formed by the control gate, the floating gate, andthe intergate dielectric is larger than an area of a capacitor formed bythe floating gate, the insulator, and the channel region, wherein: theinsulator comprises a material that has a larger electron affinity thansilicon dioxide; and the floating gate comprises polycrystalline ormicrocrystalline silicon carbide.
 35. A memory cell comprising: a sourceregion in a substrate; a drain region in the substrate; a channel regionin the substrate between the source region and the drain region; aninsulator comprising a material that has a larger electron affinity thansilicon dioxide; a floating gate separated from the channel region bythe insulator, the floating gate comprising a material that has anelectron affinity less than or equal to 2.7 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.7 eV; and a control gate separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide. 36.A memory cell comprising: a source region in a substrate; a drain regionin the substrate; a channel region in the substrate between the sourceregion and the drain region; an insulator comprising a material that hasa larger electron affinity than silicon dioxide; a floating gateseparated from the channel region by the insulator, the floating gatecomprising a material that has a smaller electron affinity thanpolycrystalline silicon and a barrier energy between the floating gateand the insulator being less than approximately 3.3 eV; and a controlgate separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide, wherein: the insulator comprisesamorphous silicon carbide; the barrier energy is less than approximately2.0 eV; the floating gate comprises polycrystalline or microcrystallinesilicon carbide; and an area of a capacitor formed by the control gate,the floating gate, and the intergate dielectric is larger than an areaof a capacitor formed by the floating gate, the insulator, and thechannel region.
 37. A memory cell comprising: a source region in asubstrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; a floatinggate separated from the channel region by an insulator, the floatinggate comprising a material that has an electron affinity less than orequal to 2.7 eV and a barrier energy between the floating gate and theinsulator being less than approximately 1.8 eV, the insulator having alarger electron affinity than silicon dioxide; and a control gateseparated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 38. A memory cell comprising: a sourceregion in a substrate; a drain region in the substrate; a channel regionin the substrate between the source region and the drain region; afloating gate separated from the channel region by an insulator, thefloating gate comprising a material that has a smaller electron affinitythan polycrystalline silicon and a barrier energy between the floatinggate and the insulator being less than approximately eV, the insulatorhaving a larger electron affinity than silicon dioxide; and a controlgate separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide, wherein: the floating gate comprisespolycrystalline or microcrystalline silicon carbide; the barrier energyis less than approximately 2.0 eV; and an area of a capacitor formed bythe control gate, the floating gate, and the intergate dielectric islarger than an area of a capacitor formed by the floating gate, theinsulator, and the channel region.
 39. A memory cell comprising: asource region in a substrate; a drain region in the substrate; a channelregion in the substrate between the source region and the drain region;a floating gate separated from the channel region by an insulator, thefloating gate being conductively doped and comprising a material thathas an electron affinity less than 2.7 eV and a barrier energy betweenthe floating gate and the insulator being less than approximately 1.8eV, the insulator having a larger electron affinity than silicondioxide; a control gate separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide; and wherein an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region.
 40. A memory cellcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate being conductively doped andcomprising a material that has a smaller electron affinity thanpolycrystalline silicon and a barrier energy between the floating gateand the insulator being less than approximately 3.3 eV, the insulatorhaving a larger electron affinity than silicon dioxide; a control gateseparated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide; and wherein an area of a capacitorformed by the control gate, the floating gate, and the intergatedielectric is larger than an area of a capacitor formed by the floatinggate, the insulator, and the channel region, wherein: the barrier energyis less than approximately 2.0 eV; and the floating gate comprisespolycrystalline or microcrystalline silicon carbide.
 41. A memory cellcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate comprising a material that has anelectron affinity less than or equal to 2.5 eV and a barrier energybetween the floating gate and the insulator being less thanapproximately 1.6 eV; and a control gate separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide. 42.A memory cell comprising: a source region in a substrate; a drain regionin the substrate; a channel region in the substrate between the sourceregion and the drain region; a floating gate separated from the channelregion by an insulator, the floating gate comprising a material that hasa smaller electron affinity than polycrystalline silicon and a barrierenergy between the floating gate and the insulator being less thanapproximately 2.0 eV; and a control gate separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide,wherein: the insulator comprises a material that has a larger electronaffinity than silicon dioxide; the floating gate comprisespolycrystalline or microcrystalline silicon carbide; and an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region.
 43. A memorydevice comprising: a plurality of memory cells, each memory cellcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; an insulator comprising a material that has alarger electron affinity than silicon dioxide; a floating gate separatedfrom the channel region by the insulator, the floating gate comprising amaterial that has an electron affinity less than or equal to 2.7 eV anda barrier energy between the floating gate and the insulator being lessthan approximately 1.7 eV; and a control gate separated from thefloating gate by an intergate dielectric, the intergate dielectrichaving a permittivity that is higher than a permittivity of silicondioxide.
 44. A memory device comprising: a plurality of memory cells,each memory cell comprising: a source region in a substrate; a drainregion in the substrate; a channel region in the substrate between thesource region and the drain region; an insulator comprising a materialthat has a larger electron affinity than silicon dioxide; a floatinggate separated from the channel region by the insulator, the floatinggate comprising a material that has a smaller electron affinity thanpolycrystalline silicon and a barrier energy between the floating gateand the insulator being less than approximately 3.3 eV, and a controlgate separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide, wherein: the insulator comprisesamorphous silicon carbide; the barrier energy is less than approximately2.0 eV; and the floating gate comprises polycrystalline ormicrocrystalline silicon carbide; an area of a capacitor formed by thecontrol gate, the floating gate, and the intergate dielectric is largerthan an area of a capacitor formed by the floating gate, the insulator,and the channel region; and the memory device further comprises: a rowdecoder; a column decoder; a command and control circuit; a voltagecontrol circuit; and wherein the memory cells are arranged in an array.45. A memory device comprising: a plurality of memory cells, each memorycell comprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate comprising a material that has anelectron affinity less than 2.7 eV and a barrier energy between thefloating gate and the insulator being less than approximately 1.8 eV,the insulator having a larger electron affinity than silicon dioxide;and a control gate separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide.
 46. A memory devicecomprising: a plurality of memory cells, each memory cell comprising: asource region in a substrate; a drain region in the substrate; a channelregion in the substrate between the source region and the drain region;a floating gate separated from the channel region by an insulator, thefloating gate comprising a material that has a smaller electron affinitythan polycrystalline silicon and a barrier energy between the floatinggate and the insulator being less than approximately 3.3 eV, theinsulator having a larger electron affinity than silicon dioxide; and acontrol gate separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide, wherein: the barrierenergy is less than approximately 2.0 eV; the floating gate comprisespolycrystalline or microcrystalline silicon carbide; an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region; and the memorydevice further comprises: a row decoder; a column decoder; a command andcontrol circuit; a voltage control circuit; and wherein the memory cellsare arranged in an array.
 47. A memory device comprising: a plurality ofmemory cells, each memory cell comprising: a source region in asubstrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; a floatinggate separated from the channel region by an insulator, the floatinggate comprising a material that has an electron affinity less than orequal to 2.5 eV and a barrier energy between the floating gate and theinsulator being less than approximately 1.6 eV; and a control gateseparated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 48. A memory device comprising: aplurality of memory cells, each memory cell comprising: a source regionin a substrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; a floatinggate separated from the channel region by an insulator, the floatinggate comprising a material that has a smaller electron affinity thanpolycrystalline silicon and a barrier energy between the floating gateand the insulator being less than approximately 2.0 eV; and a controlgate separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide, wherein: the floating gate comprisespolycrystalline or microcrystalline silicon carbide; the insulatorcomprises a material that has a larger electron affinity than silicondioxide; an area of a capacitor formed by the control gate, the floatinggate, and the intergate dielectric is larger than an area of a capacitorformed by the floating gate, the insulator, and the channel region; andthe memory device further comprises: a row decoder; a column decoder; acommand and control circuit; a voltage control circuit; and wherein thememory cells are arranged in an array.
 49. A memory device comprising: aplurality of memory cells, each memory cell comprising: a source regionin a substrate; a drain region in the substrate; a channel region in thesubstrate between the source region and the drain region; a floatinggate separated from the channel region by an insulator, the floatinggate being conductively doped and comprising a material that has anelectron affinity less than 2.7 eV and a barrier energy between thefloating gate and the insulator being less than approximately 1.8 eV,the insulator having a larger electron affinity than silicon dioxide; acontrol gate separated from the floating gate by an intergatedielectric, the intergate dielectric having a permittivity that ishigher than a permittivity of silicon dioxide; and wherein an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region.
 50. A memorydevice comprising: a plurality of memory cells, each memory cellcomprising: a source region in a substrate; a drain region in thesubstrate; a channel region in the substrate between the source regionand the drain region; a floating gate separated from the channel regionby an insulator, the floating gate being conductively doped andcomprising a material that has a smaller electron affinity thanpolycrystalline silicon and a barrier energy between the floating gateand the insulator being less than approximately 3.3 eV, the insulatorhaving a larger electron affinity than silicon dioxide; a control gateseparated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide; and wherein an area of a capacitorformed by the control gate, the floating gate, and the intergatedielectric is larger than an area of a capacitor formed by the floatinggate, the insulator, and the channel region, wherein: the barrier energyis less than approximately 2.0 eV; the floating gate comprisespolycrystalline or microcrystalline silicon carbide; and the memorydevice further comprises: a row decoder; a column decoder; a command andcontrol circuit; a voltage control circuit; and wherein the memory cellsare arranged in an array.
 51. The memory device of claim 18, furthercomprising: a row decoder; a column decoder; a command and controlcircuit; a voltage control circuit; and wherein the memory cells arearranged in an array.
 52. A memory cell comprising: a storage electrodeto store charge, the storage electrode being conductively doped andcomprising a material that has a smaller electron affinity thanpolycrystalline silicon; an insulator adjacent to the storage electrode,wherein a barrier energy between the insulator and the storage electrodeis less than approximately 3.3 eV, the insulator having a largerelectron affinity than silicon dioxide; and a control electrode,separated from the storage electrode by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 53. The memory cell of claim 52,further comprising: a source region in a substrate; a drain region inthe substrate; a channel region in the substrate between the sourceregion and the drain region; and wherein the insulator is between thestorage electrode and the channel region; and wherein an area of acapacitor formed by the control electrode, the storage electrode, andthe intergate dielectric is larger than an area of a capacitor formed bythe storage electrode, the insulator, and the channel region.
 54. Amemory device comprising: a plurality of memory cells, wherein eachmemory cell includes a transistor comprising: a source region; a drainregion; a channel region between the source and drain regions; afloating gate separated from the channel region by an insulator, thefloating gate comprising a material that has an electron affinity lessthan or equal to 2.7 eV and a barrier energy between the floating gateand the insulator being less than approximately 1.8 eV, the insulatorhaving a larger electron affinity than silicon dioxide; and a controlgate separated from the floating gate by an intergate dielectric, theintergate dielectric having a permittivity that is higher than apermittivity of silicon dioxide.
 55. The memory device of claim 54wherein: the floating gate comprises polycrystalline or microcrystallinesilicon carbide; an area of a capacitor formed by the control gate, thefloating gate, and the intergate dielectric is larger than an area of acapacitor formed by the floating gate, the insulator, and the channelregion; and the memory device further comprises: a row decoder; a columndecoder; a command and control circuit; a voltage control circuit; andwherein the memory cells are arranged in an array.
 56. A memory devicecomprising: a plurality of memory cells, wherein each memory cellincludes a transistor comprising: a source region; a drain region; achannel region between the source and drain regions; a floating gateseparated from the channel region by an insulator, the floating gate anelectron affinity less than or equal to 2.6 eV, the floating gate beingcapacitively separated from the channel region to providetransconductance gain, the insulator having a larger electron affinitythan silicon dioxide; and a control gate separated from the floatinggate by an intergate dielectric, the intergate dielectric having apermittivity that is higher than a permittivity of silicon dioxide. 57.A memory device comprising: a plurality of memory cells, wherein eachmemory cell includes a transistor comprising: a source region; a drainregion; a channel region between the source and drain regions; afloating gate separated from the channel region by an insulator, thefloating gate being capacitively separated from the channel region toprovide transconductance gain, the insulator having a larger electronaffinity than silicon dioxide; and a control gate separated from thefloating gate by an intergate dielectric, the intergate dielectrichaving a permittivity that is higher than a permittivity of silicondioxide, wherein: the floating gate comprises polycrystalline ormicrocrystalline silicon carbide and has a smaller electron affinitythan polycrystalline silicon; a barrier energy between the floating gateand the insulator is less than approximately 3.3 eV; an area of acapacitor formed by the control gate, the floating gate, and theintergate dielectric is larger than an area of a capacitor formed by thefloating gate, the insulator, and the channel region; and the memorydevice further comprises: a row decoder; a column decoder; a command andcontrol circuit; a voltage control circuit; and wherein the memory cellsare arranged in an array.